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Lottery Simulation-Profit Or Loss-Part 05, by Sudarshan Iyengar

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Lottery Simulation-Profit Or Loss-Part 06, by Sudarshan Iyengar

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Lottery Simulation-Profit Or Loss, by Sudarshan Iyengar

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Lower Bounds Lock Free Synchronization,Load Stealing, by Subodh Kumar

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Lstm, by Ramaseshan R

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Machine Learning Algorithm K-Means Using Map Reduce for Big Data Analytics, by Rajiv Misra

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Machine Learning, Perceptron, Linearly Separable, by Ramaseshan R

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Machine Translation, by Ramaseshan R

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Magic Square Hit and Trial 01, by Sudarshan Iyengar

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Magic Square Hit and Trial 02, by Sudarshan Iyengar

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Magic Square Hit and Trial 03, by Sudarshan Iyengar

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Magic Square Hit and Trial 04, by Sudarshan Iyengar

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Magic Square Hit and Trial 05, by Sudarshan Iyengar

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Mapping the Output Layer to Softmax, by Ramaseshan R

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MapReduce Examples, by Rajiv Misra

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Matrix Operations Explained, by Ramaseshan R

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Matrix, by Ragunathan Rengasamy

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Max Flow is P-Complete for NC-Reductions, by Sajith Gopalan

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Memory Consistency & Performance Issues, by Subodh Kumar

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Memory Consistency, by Subodh Kumar

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Mesh of Trees, Hypercube, by Sajith Gopalan

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Model Checking Algorithm, by Santosh Biswas

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Modeling Epidemics on Complex Networks, by Sudarshan Iyengar

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Modeling Techniques – 1, by Prof.Arnab Sarkar

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Modeling Techniques – 2, by Prof.Arnab Sarkar

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Models of Parallel Computation,Complexity, by Subodh Kumar

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Modern Ethernet, by Sujoy Ghosh

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Module 1.1: Introduction to the Course, by V. Kamakoti

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Module 1.2: CMOS Transistors and Gates, by V. Kamakoti

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Module 1.3: Basic Gates, by V. Kamakoti

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Module 1.4: Building Gates Using Simulator, by V. Kamakoti

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Module 1.5: Hierarchical Design and Verification, by V. Kamakoti

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Module 1.6: Building Blocks of a Digital Computer, by V. Kamakoti

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Module 2.1: Binary Number Systems, by V. Kamakoti

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Module 2.2: Signed Number Systems, by V. Kamakoti

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Module 2.3: Two’S Complement Number System, by V. Kamakoti

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Module 2.4: Binary Adder Circuits, by V. Kamakoti

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Module 2.5: Building the ALU of HACK, by V. Kamakoti

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Module 2.6: HACK ALU Functionality, by V. Kamakoti

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Module 3.1: Sequential Logic Design, by V. Kamakoti

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Module 3.2: Latches and Flipflops, by V. Kamakoti

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Module 3.3: The Memory Hierarchy, by V. Kamakoti

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Module 3.4: Design of Program Counter, by V. Kamakoti

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Module 3.5: Introduction to Computer Organization: The HACK Instruction Set Architecture (ISA), by V. Kamakoti

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Module 3.6 Memory Mapped I/O, by V. Kamakoti

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Module P1: Tips for Project P01, by V. Kamakoti

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Module P2: Tips for Projects P02 and P03, by V. Kamakoti

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Module P3: Tips for Project 04, by V. Kamakoti

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Module P4: Tips for Project 04, by V. Kamakoti

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Monte Hall : 3 Doors and a Twist 01, by Sudarshan Iyengar

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